Estudio comparativo del efecto de tiempos muertos y pérdidas en topologías NPC y NPP
Loading...
Date
2026
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Universidad de Concepción
Abstract
El tiempo muerto es un periodo de espera a la hora de encender un dispositivo semiconductor, impuesto a fin de evitar disparos de corriente directa en fuentes de voltaje. En diversas investigaciones se han analizado los efectos que este periodo provoca en los inversores de potencia, estos análisis se han enfocado en un tiempo muerto reducido. Esta investigación busca analizar los efectos que presentan diferentes valores de tiempo muerto en los inversores multinivel NPP y NPC, dos de los inversores multinivel más utilizados en aplicaciones de generación fotovoltaica. A partir del software PLECS, se realizó un modelo de los inversores mediante la modulación SPWM, utilizando las portadoras en disposición de fase. Se realizó una comparativa de dos métodos de implementación del tiempo muerto, donde la primera opción consistía en un apagado total de los semiconductores de la fase durante el periodo de tiempo muerto y la segunda opción, donde se apagan únicamente los switches complementarios. Llegando a la primera conclusión de que, pese a ser los dos métodos efectivos en la redirección de la corriente, un apagado total de la fase durante los periodos de tiempo muerto implicaba saltos de 𝑉𝑑𝑐 durante los tiempos muertos, mientras que el apagado único de los switches complementarios implicaba saltos de 𝑉𝑑𝑐2 durante el mismo periodo, siendo esta la mejor configuración. Se procedió con la implementación de los perfiles térmicos de los semiconductores, realizando versiones de los inversores mediante la utilización de IGBTs y MOSFETs. A fin de realizar una corroboración de los resultados se realizaron versiones más realistas, mediante la utilización de las versiones con límites di/dt de los semiconductores, las cuales entregaron datos semejantes. Para realizar los encadenamientos de simulaciones junto con la recolección de datos se implementó una programación dentro de PLECS la cual realizaba modificaciones de factores de potencia y tiempo muerto en la simulación, al finalizar el proceso guardaba los resultados de interés en archivos .CSV. A partir de los modelos se obtiene que el inversor NPC presenta un THD I levemente menor que la topología NPP en tiempos muertos menores a 15μs, mientras que para tiempos muertos altos (> 15μs que en la práctica no se usa) el THD I de NPP es contrariamente menor. El NPP mostró una eficiencia 0.22% mayor en todos los casos. El inversor NPC entregó un voltaje de modo común y corriente de fuga 0.28% menor en configuraciones basadas en IGBT.
Dead time is the waiting period when you are switching a Semiconductor Device, Imposed to prevent direct current shoots-through in voltage sources. Various studies have analysed the effects this period causes in power inverters. Focusing on reduced dead time values. This research aims to analyze the effects that are shown by the different dead time values in NPP and NPC multilevel inverters. Two of the most widely used multilevel inverters in photovoltaic power generation. Based on the PLECS software, a model of the inverters was made using the SPWM modulation carrier in phase disposition. A comparison of two dead time implementation methods was done: the first involved a total shutdown of phase semiconductors during the dead time period. The second involved shutting down only the complementary switches. It was concluded that, although both methods are effective in redirecting current, a total shutdown resulted in voltage jumps of 𝑉𝑑𝑐 during dead times, while shutting down only the complementary switches resulted in jumps of 𝑉𝑑𝑐2. Making this one the best configuration. The research proceeded with the implementation of thermal profiles for the semiconductors, creating versions of the inversos using IGBTs and MOSEFETs. To corroborate the results realistic versions were developed using semiconductor models with di/dt limits, which provided similar data. To do the simulation chains and data collection a script was implemented within de PLECS to modify power factors and dead time values during the simulation. At the end of the process relevant results in .CVS were stored. Based on the models, it was found that an NPC inverter presents a slightly lower THD I than NNP topology for dead times under 15μs. whilst for high dead times (>15μs which are not used in practice), the NPP’s THD I is conversely lower. NPP showed a 0.22% higher efficiency in all cases. The NPC inverter delivered a common-mode voltage and leakage current 0.28% lower in IGBT-based configurations.
Dead time is the waiting period when you are switching a Semiconductor Device, Imposed to prevent direct current shoots-through in voltage sources. Various studies have analysed the effects this period causes in power inverters. Focusing on reduced dead time values. This research aims to analyze the effects that are shown by the different dead time values in NPP and NPC multilevel inverters. Two of the most widely used multilevel inverters in photovoltaic power generation. Based on the PLECS software, a model of the inverters was made using the SPWM modulation carrier in phase disposition. A comparison of two dead time implementation methods was done: the first involved a total shutdown of phase semiconductors during the dead time period. The second involved shutting down only the complementary switches. It was concluded that, although both methods are effective in redirecting current, a total shutdown resulted in voltage jumps of 𝑉𝑑𝑐 during dead times, while shutting down only the complementary switches resulted in jumps of 𝑉𝑑𝑐2. Making this one the best configuration. The research proceeded with the implementation of thermal profiles for the semiconductors, creating versions of the inversos using IGBTs and MOSEFETs. To corroborate the results realistic versions were developed using semiconductor models with di/dt limits, which provided similar data. To do the simulation chains and data collection a script was implemented within de PLECS to modify power factors and dead time values during the simulation. At the end of the process relevant results in .CVS were stored. Based on the models, it was found that an NPC inverter presents a slightly lower THD I than NNP topology for dead times under 15μs. whilst for high dead times (>15μs which are not used in practice), the NPP’s THD I is conversely lower. NPP showed a 0.22% higher efficiency in all cases. The NPC inverter delivered a common-mode voltage and leakage current 0.28% lower in IGBT-based configurations.
Description
Tesis presentada para optar al título de Ingeniero/a Civil Electrónico/a.
Keywords
Electromagnetismo, Semiconductores, Topología